HKEPC reported that a 144-page document containing specifications for Strix Point processors and Strix Halo-based Ryzen processors has been leaked. AMD has yet to reveal details of its next-generation Zen 5 APUs, but thanks to the leak, a lot of interesting things have been revealed.
The Strix Point (STX) 12 Zen comes with 5 cores and 24 threads, and will also have 12MB L2 cache and 24MB L3 cache. This APU will have 8 WGPs based on the RDNA3.5 architecture, which correspond to 16 computing units. The XDNA2 AI-Accelerator delivers 50 points higher, which is three times faster than Hawk Point. The APU will support DisplayPort 2.1 specifications, even in UHBR10 transport mode. The Strix Point is expected to have a TDP of 45-65W and will use the FP8 socket.
According to the document, the Strix Halo (STX Halo) will be a 16-core, 32-thread product. Like the STX, this model also gets 1MB per core, which means 16MB of L2 cache and 32MB of L3 cache. Additionally, the Strix Halo will also include a 32MB MALL cache, which will function similarly to the Infinity Cache. The APU will support the XDNA2 processor developed for artificial intelligence, which can deliver up to 60 TOPS. It will also support DisplayPort 2.1 up to UHBR20 mode, and we can expect a 70-130W product that uses the FP11 socket. Judging from the chip, the Halo supports 256-bit LPDDR5X-8000 memory, while the Point supports up to LPDDR5x-7500 memory.
AMD is already gearing up for Computex, where the Zen 5 series for desktop and mobile could be discussed, so hopefully we'll learn more about the Ryzen 9000, i.e. the Strix series, at the latest.
